Verilog Code For Serial Adder Subtractor Using Logic Gates

Basic Logic Design with Verilog TA: Chihhao Chao chihhao@access.ee.ntu.edu.tw Lecture note ver.1 by Chen-hanTsai. RTL Code Gate Level Code Physical Layout Tape Out Designer Level High Low Cost Low. Adder Adder Adder Adder_tree instance example.

Contents • • • • • • • • • • • • • • • Full-Adder in Verilog Review A full adder is a combinational logic that takes 3 bits, a, b, and carry-in, and outputs their sum, in the form of two bits, carry-out, and sum. The figure below illustrates the circuit: New Project • The first task is start the Xilinx ISE and create a New Project. Let's call it FourBitAdder.

• Once the Project is created, add a New Source, of type Verilog Module. Call it SingleStage. It will contain the full-adder for 2 bits. • Define the ports as follows: • a, input • b, input • cin, input • s, output • cout, output We now have several options to define this adder.

One is functional, as illustrated in the next subsection. Next is a logical description, where we express the outputs in terms of their logical equation. The final is a gate level description.

Pick the one that seem most interesting to you. They should all yield the same result in the next section, where we test them. Functional Description of Full Adder. Module MultiStages ( input [ 3: 0 ] a, input [ 3: 0 ] b, output [ 3: 0 ] sum, output carry ); wire cin; assign cin = 1 'b0; SingleStage s0 (. A ( a [ 0 ] ),.

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B ( b [ 0 ]),. Cin ( cin ),. S ( sum [ 0 ]),. The rafael mendez collection pdf viewer free. Cout ( ripple0 ) ); SingleStage s1 (. A ( a [ 1 ] ),. B ( b [ 1 ]),.

Cin ( ripple0 ),. S ( sum [ 1 ]),.

Cout ( ripple1 ) ); SingleStage s2 (. A ( a [ 2 ] ),. B ( b [ 2 ]),. Cin ( ripple1 ),. S ( sum [ 2 ]),. Cout ( ripple2 ) ); SingleStage s3 (.

A ( a [ 3 ] ),. B ( b [ 3 ]),. Cin ( ripple2 ),. S ( sum [ 3 ]),. Cout ( carry ) ); endmodule • Check the syntax of your module and fix any bugs you discover! Explanations wire cin assign cin = 1'b0 The first stage of the adder, the one adding the Least Significant bits should have a 0 coming in on its carry-in input. This is done by creating this wire, which we set equal to 0 all the time in the next statement.

The 1'b0 notation means 1 bit, with binary value 0. SingleStage(.cout( ripple1 ).) SingleStage(.cin( ripple1 ).) The carry-out of one stage is directly connected to the carry-in of the next stage. We need a wire for this purpose. We could have defined ripple1 as a wire, but Verilog allows one to not declare wires that are internal to the circuit, connecting one block to another. Test Module • Add a New Source file of type Verilog Test Fixture and call it test4. • Attach it to MultiStages • Edit the module as shown below.